1. Field of the Invention
The present invention relates generally to electronic fuse structures provided in integrated circuits, and particularly, a system and method for fabricating scalable electronic fuse structures employed for fixing configuration of IC circuit components and enhancing IC circuit performance.
2. Discussion of the Prior Art
Currently, metal fuses may be fabricated in integrated circuits for a variety of reasons, including protection from ESD during manufacture and handling during burn-in or prior to packaging, removing or disconnecting defective components from a circuit, or, for generating initial values of stored data, e.g., in an IC ROM.
U.S. Pat. No. 4,272,753 discusses a method for fabricating a discrete metallic fuse device using fusable material which is necked to a narrow region. The fusable material is separated from an insulative layer by an air gap which provides lower thermal conductivity environment.
U.S. Pat. No. 4,089,734 discusses a metallic fuse device for read only memory and memory reconfiguration applications which involves a complicated technique including a four layer deposition of metallizations, requires the etching at two sides of a fusable link layer to form the resultant fusable link, and etching of the silicon substrate material to form a mesa structure.
U.S. Pat. No. 4,879,587 discusses manufacture of a metallic fuse device that is provided on top of a supporting insulating bridge structure for connecting two conductive regions.
The manufacture of each of these fuse devices in the prior art is generally complicated requiring many processing steps.
It is thus highly desirable to provide a system and method for manufacturing a scalable electronic fuse structure in an integrated circuit, and particularly, that may function at any level of wiring, in a minimum of process steps. Such a novel fuse structure for an integrated circuit may be scaled, i.e., tailored to fix configuration of IC circuit components.
It would additionally be highly desirable to provide a system and method for manufacturing a high-performance conducting line comprising a gap conductor, i.e., a conductor partially or completely exposed in an air-gap region, which is designed to enhance IC circuit performance by providing lower capacitive conducting line loading.
It is an object of the present invention to provide a scalable electronic fuse structure in integrated circuits and a method for manufacturing thereof that comprises a gap conductor, i.e., a conductor partially or completely exposed in an air-gap region, with the minimum of process steps.
It is a further object of the present invention to provide a novel high-performance signal line structure in integrated circuits and a method for manufacture thereof that is designed and tailored to minimize inter level signal capacitive loading.
The present invention solves the problem of removing an inter level dielectric selective to an overpassing conductor, and leaving an air gap between the conductor and the structure below, in a minimum of process steps. Thus, the present invention provides a solution to two known problems: 1) the minimization of inter level signal wiring capacitance with a material that has a low dielectric constant, e.g., an air gap; and, 2) locally minimizing the thermal conduction path below a conductor to the silicon substrate. The general method used to remove the underlying dielectric of an overpassing metal conducting line, e.g., aluminum or copper line, is to add one blockout mask to the process used to etch the region under the conductor.
Particularly, the method for manufacturing an electronic fuse device for an integrated circuit comprises the steps of: providing a semiconductor substrate having at least an interlevel dielectric layer formed thereon; forming an underfill layer of material in the interlevel dielectric layer above the substrate at a location corresponding to a location of an overpassing conducting line; forming a metal conductor on top of the underfill layer, so that the underfill layer has a width greater than a width of the conductor; providing additional interlevel insulating dielectric material over the conductor; forming a via structure extending through the interlevel insulating dielectric and extending to a portion of the underfill layer extending past the conductor; and, through the via, etching the underfill layer to form a resultant air gap formed within the interlevel dielectric, wherein the conductor is partially exposed in the air gap between the substrate.
Advantageously, the employment of the novel electronic fuse structure according to the invention enables employment of BEOL wiring for electronic fuses. Furthermore, the electronic fuse structure may be scaled to dimensions smaller than that of a laser beam, which are currently used to blow conventional large and cumbersome electronic laser fuses.